1. Field of the Invention
The present invention relates to a method of fabricating a low temperature polysilicon thin film transistor (LTPS TFT), and more particularly, to a method of fabricating a low temperature polysilicon thin film transistor with good electrical characteristics and good reliability performance.
2. Description of the Prior Art
Nowadays, a liquid crystal display (LCD) is the most mature flat panel display technique. The applications for a liquid crystal display are extensive, such as mobile phones, digital cameras, video cameras, notebooks, and monitors. Due to the high vision quality requirements and the expansion of new application fields, the LCD is developed toward high quality, high resolution, high brightness, and low price. The low temperature polysilicon thin film transistor (LTPS TFT), having a character of being actively driven, is a break-through in achieving the above objective.
Please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematic diagrams of fabricating a low temperature polysilicon thin film transistor 26 according to the prior art. The prior art low temperature polysilicon thin film transistor 26 is fabricated on an insulation substrate 10. The insulation substrate 10, composed of transparent materials, may be a glass substrate or a quartz substrate.
Referring to FIG. 1, an amorphous silicon thin film (α-Si thin film, not shown) is formed on a surface of the insulation substrate 10 first. Then an excimer laser annealing (ELA) process is performed to re-crystallize the amorphous silicon thin film (not shown) into a polysilicon layer 12. A source region 13, a drain region 14, and a channel region 15 are comprised on a surface of the polysilicon layer 12.
Since the quality of the amorphous silicon thin film (not shown) is a determinative factor for the characteristics of the subsequent formed polysilicon layer 12, all of the parameters during the amorphous silicon thin film deposition process need to be strictly controlled. The amorphous silicon thin film with low hydrogen content, high thickness uniformity, and low surface roughness is thus formed. Moreover, the amorphous silicon thin film is melted and re-crystallized rapidly through absorption of the deep ultraviolet light during the excimer laser annealing process to form the polysilicon layer 12. Such a quick absorption due to the short laser pulse only affects the surface of the amorphous silicon thin film and will not affect the insulation substrate 10. Hence, the insulation substrate 10 is kept at a low temperature state.
As shown in FIG. 2, a plasma enhanced chemical vapor deposition (PECVD) process is thereafter performed to form a silicon oxide layer (SiOx layer, x≈2) 16 having a thickness of 500˜1200 angstrom (Å) on the surface of the polysilicon layer 12. Since the molecules of the participating gases, such as silane (SiH4) and nitrous oxide (N2O), are dissociated into atoms, ions, or radicals by plasma to proceed the deposition reaction for the silicon oxide layer 16, the silicon oxide layer 16 is also called a silane-based silicon oxide (SiH4 based SiOx) layer. After that, a first sputtering process is performed to form a metal layer 18 on a surface of the silicon oxide layer 16. The metal layer 18 may be a tungsten (W) layer, a chrome (Cr) layer, or another conductive metal layer.
As shown in FIG. 3, then a photoresist layer (not shown) is formed on the surface of the insulation substrate 10. A photolithography process is thereafter performed to define a gate pattern 22 in the photoresist layer (not shown). The gate pattern 22 is on top of the channel region 15. After that, a dry etch process is performed to remove portions of the metal layer 18 so as to form a gate 24 on top of the silicon oxide layer 16. The silicon oxide layer 16 is used as a gate insulating layer of the low temperature polysilicon thin film transistor.
After removing the gate pattern 22, an ion implantation process is then performed to form a source 28 and a drain 32 of the low temperature polysilicon thin film transistor 26, in the source region 13, and in the drain region 14 in the polysilicon layer 12 respectively by utilizing the gate 24 as a mask, as shown in FIG. 4. In consideration to the application of the thin film transistor (TFT), the series resistance of the source/drain must be low. An activation process is thus necessarily performed after the ion implantation process to highly activate the dopants in the source 28 and the drain 32. The activation process not only moves the ions to the correct lattice sites but also repairs the lattice defects incurred from the ion implantation process to complete the fabrication of the low temperature polysilicon thin film transistor 26.
After completing the low temperature polysilicon thin film transistor 26 a dielectric layer 34 is deposited. The dielectric layer 34 may be a single-layered dielectric layer or a composite-layered dielectric layer. Finally a photo-etching-process (PEP) is performed to form a contact hole 36 from the dielectric layer 34 and the silicon oxide layer 16, on top of the source region 13 and the drain region 14, extending to the source 28 and the drain 32, respectively. The contact hole 36 is filled with conductive materials to electrically connect the source 28 and the drain 32 to the electrode of the capacitor and the signal line respectively, according to the circuit design.
However, the prior art method of fabricating a low temperature polysilicon thin film transistor 26 incurs a severe problem. The silane-based silicon oxide (SiH4-based SiOx) thin film, deposited by the PECVD process, contains an eminent amount of hydrogen (H). The hydrogen content is from 2˜9 atomic % depending on the processing parameters. The hydrogen content comes from Si—H bonds, which form when a precursor in the plasma with a low dissociation temperature loses hydrogen atoms to unsaturated silicon (S) atoms. The diffusion velocity of hydrogen atoms is rapid due to their small size. As a result, the hydrogen atoms are readily diffused into the Si—SiO2 interface. Owing to the discontinuous property of the Si—SiO2 interface, H atoms are trapped in the Si—SiO2 interface and become interface-trapped charges (Qit). Basically, the interface trapped charges can be reduced by using an adequate annealing process. However, the interface traps cannot be eliminated completely.
Please refer to FIG. 5 that is a schematic diagram of another low temperature polysilicon thin film transistor 56 according to the prior art. The prior art low temperature polysilicon thin film transistor 56 is similar to the low temperature polysilicon thin film transistor 26 in FIG. 4. The difference between them is the silicon oxide layer 16, used as the gate insulating layer in the low temperature polysilicon thin film transistor 56, is replaced with a tetra-ethyl-ortho-silicate based silicon oxide layer (TEOS-based SiOx layer) 46. The tetra-ethyl-ortho-silicate based silicon oxide layer 46 is a silicon oxide thin film deposited by PECVD by inputting tetra-ethyl-ortho-silicate (TEOS) and oxygen. The silicon oxide thin film 46, formed by this method, has better interface property than the silane-based silicon oxide thin film 16 deposited by the PECVD process. Moreover, the step coverage ability of the silicon oxide thin film, formed by this method, is better than the silane-based silicon oxide thin film deposited by the PECVD process.
Since the silicon oxide layer 46 in the low temperature polysilicon thin film transistor 56 is composed of the tetra-ethyl-ortho-silicate based silicon oxide, the interface property is obviously improved to inhibit the generation of the interface trapped charges. The flat band voltage (VFB) for the low temperature polysilicon thin film transistor 56 is thus lowered. For any low temperature polysilicon thin film transistor, the threshold voltage (Vt) correlates closely to the flat band voltage. Therefore, the silicon oxide layer 46 composed of tetra-ethyl-ortho-silicate based silicon oxide improves the stability of the threshold voltage for the low temperature polysilicon thin film transistor 56 effectively. However, the breakdown field strength for the silicon oxide layer 46 is not high. In view of the device performance, this film is not ideal.
Please refer to FIG. 6. FIG. 6 is a schematic diagram of another low temperature polysilicon thin film transistor 86 according to the prior art. The prior art low temperature polysilicon thin film transistor 86 is also similar to the low temperature polysilicon thin film transistor 26 in FIG. 4. The difference between them is the gate insulating layer 76 is a composite layer composed of a silane-based silicon oxide layer 77 and a silicon nitride layer 79 in the low temperature polysilicon thin film transistor 86. A PECVD process is performed to form the silane-based silicon oxide layer 77. Another PECVD process is afterwards performed to form a silane-based silicon nitride (SiH4-based SiNx) layer 79 by inputting silane, ammonia (NH3), and nitrogen (N2) on a surface of the silicon oxide layer 77. In comparison with the silicon oxide thin film, the silicon nitride layer 79 has a better moisture barrier ability, a better metal ions barrier ability, and a higher breakdown field strength to endow the low temperature polysilicon thin film transistor 86 with better electrical characters and high reliability.
However, the prior art method of fabricating a low temperature polysilicon thin film transistor can not fabricate a low temperature polysilicon thin film transistor having a good interface property, a good threshold voltage stability, a good barrier ability for moisture and metal ions and a high breakdown voltage. Therefore, it is very important to fabricate a low temperature polysilicon thin film transistor with the above-mentioned advantage.